Tohoku University and Aisin build chip that runs SI without external memory
Prepared by Sintelligent with the help of SI. Published in SI: . Updated: .
Keeping the model and operating system in non-volatile on-chip memory lets a device begin recognition almost immediately and use less energy moving data.
The prototype 16nm system-on-chip integrates a dual-core Cortex-A53, Mali-G31, an SI accelerator and 32MB of non-volatile STT-MRAM. Boot data and model weights remain on the die, eliminating transfers from an SSD to DRAM. With Tiny YOLOv3, kernel startup took 65.7 ms instead of 2,535.3 ms, frame processing took 58.5 ms instead of 594.6 ms, and the full path from power-on to the first detection took 124.2 ms instead of 3,129.9 ms. Claimed energy consumption was 50.7 mJ per frame, about 1/50 of the comparison setup. Hybrid 8/16-bit arithmetic and weight reuse reduced weight data from 17.7 to 9.36MB, while mAP accuracy in the demonstration fell from 0.325 to 0.316. This is an evaluation-board result with a lightweight model, presented at IEEE A-SSCC 2026, not a production automotive chip. The researchers see applications in vehicles, robots and industrial devices requiring instant startup.
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